Tektronix TLA5000 Series Logic Analyzer

The affordable TLA5000 Series logic analyzers make high-speed timing resolution, deep memory acquisition, fast state acquisition and sophisticated triggering available to any digital designer who needs to identify initialization failures, operation crashes and intermittent operation. For first-time as well as experienced logic analyzer users, the TLA5000 Series is ideal for single synchronous bus state and timing analysis. An intuitive user interface, familiar Windows-based desktop and OpenChoice™ networking and analysis features make the TLA5000 Series logic analyzers easy to network into your design environment.

500 ps timing resolution with up to 32 Mb memory depth with simultaneous 125 ps MagniVuTM acquisition on each channel means you can measure digital signal timing on increasingly faster signals with confidence. With MagniVu timing resolution, find difficult problems such as digital logic errors, glitches, setup/hold violations and crosstalk quickly. Use setup/hold violation triggering and display to validate setup/hold performance of digital devices.

Today, most designs can have both digital and analog anomalies. With iView™ time-correlated, integrated analog-digital view, you’ll clearly see how analog anomalies are affecting your digital signal – right on your logic analyzer display.

Features & Benefits

• 500 ps/32 Mb Deep Memory Timing with Simultaneous 125 ps MagniVu High-resolution Timing on Each Channel to Measure Digital Signal Timing on Fast Signals with Confidence
• 235 MHz State Acquisition for Analysis of High-speed Synchronous Digital Circuits
• iView TM Time-correlated, Integrated Analog-digital View to See How Analog Anomalies are Affecting Your Digital Signals
• Validate Setup/Hold Performance of Digital Devices with Setup/Hold Violation Triggering and Display

Applications

• Digital Hardware Verification and Debug
• Monitoring and Measurement of Digital Hardware Performance
• Single Microprocessor and Bus Debug

Performance Overview

MagniVu and iView (integrated view) simultaneous with either timing or state acquisition.

• Deep Memory Timing
  Maximum Timing Resolution – 500 ps (2 GHz).
  Maximum Memory Depth – 32 Mb per channel.
• MagniVu™
  Maximum Timing Resolution – 125 ps (8 GHz).
  MagniVu Memory Depth – 16 Kb per channel.
• State Acquisition
  Maximum Clock Rate – 235 MHz.
  Maximum Memory Depth with Timestamps – 8 Mb per channel.
• iView TM Tektronix Oscilloscopes Supported
  TDS1000/2000 Series.
  TDS3000/3000B Series.
  TDS5000 Series.
  TDS6000 Series.
  CSA/TDS7000 Series.
  TDS684C, TDS694C.
  TDS754C, TDS784C, TDS724D, TDS754D, TDS784D, TDS794D.