TEK TLA711 Logic Analyzer

Features

Today's digital design engineers face daily pressures to speed new products to the marketplace. The TLA 700 Series answers the need with breakthrough solutions for the entire design team, providing the ability to quickly monitor, capture and analyze real-time system operation in order to debug, verify, optimize and validate digital systems.

Hardware developers, Hardware/Software integrators and embedded software developers will appreciate the range of capabilities of the TLA 700 Series. Its broad feature set includes capturing and correlating elusive hardware and software faults; providing simultaneous state and high-speed timing analysis; using deep state acquisition to find the cause of complex problems; generating the digital stimulus for functional verification, debugging and stress testing; and offering non-intrusive real-time software execution tracing that correlates to the source code and to the hardware events.

This kind of performance is matched by value. The TLA 700 Series consists of portable and benchtop mainframes, logic analyzer modules, pattern generator modules, digitizing oscilloscope modules, and a full line of complementary support products for popular microprocessors and buses. Productivity and connectivity features such as the open Microsoft Windows platform make the TLA 700 Series easy to use and easily networked into the design environment. Modularity and flexibility features help you protect your current investment, as well as allow you to buy what you need today and expand to meet your needs tomorrow.

The TLA 700 Series includes a wide selection of logic analyzer modules with unprecedented measurement capabilities. At the heart of these modules is a breakthrough acquisition technology called MagniVu. MagniVu is a super-high-speed sampling architecture that dramatically changes the way logic analyzers work and enables them to provide startling new measurement capabilities.

All incoming data is always oversampled at 2 GHz. The oversampled data is then processed in real-time to perform timing acquisition, state acquisition and triggering without missing crucial timing information on any channel.

Complex system problems, especially intermittent ones, that show up late in product development can derail the most carefully planned schedules. The TLA 700 Series keeps embedded hardware and software designers on track by providing a non-intrusive tool to monitor, capture and analyze these elusive real-time system problems. By capturing and correlating many aspects of software and hardware operation, the design team can quickly identify the source of the problem, wherever it is.

Problem-solving is easier with the TLA 700 Series, thanks to MagniVu acquisition technology. Because the modules always oversample incoming data at 2 GHz, they are able to provide unmatched state acquisition capabilities. The sample point for each channel can be placed anywhere from 8.5 nanoseconds before the selected clock edge to 7.0 ns after the clock edge, in 500 picosecond increments.

If your design involves sections of circuitry with different timing requirements or even mixed logic families, that's no problem for the TLA 700 Series; you can set different sample points and unique threshold settings for different groups of channels.

Each logic analyzer module has the ability to trigger on precise timing problems. Whether timing problems are suspect, or things seem to be working and you need to test for design margins, the TLA 700 Series triggering does what no other logic analyzer can.

The TLA 700 Series can trigger with 500 ps resolution on setup-and-hold time violations on any or all groups of channels. You can select different timing limits for different groups and even verify propagation delay from clock-to-output of synchronous circuits.

Not even glitches can escape the watchful eye of the TLA 700 Series, since glitch detection logic processes the same oversampled data. Any set of two or more transitions between sample points on any channel is captured, displayed and can be used for glitch triggering.

The precise timing of whatever condition you trigger on is fully visible with MagniVu oversampling technology. This means that when you trigger on a setup-and-hold time violation on a 128 bit data bus, you can immediately view all 128 channels to see exactly which signals caused the violation and how far those signals were beyond the limits you specified.

Embedded hardware designers know the frustration of trying to identify obscure real-time hardware problems in system development. These problems include logic errors, logic level violations, noise margins, crosstalk, bus contention, termination errors, clock skews, timing margins and violations, setup and hold violations and glitches. The TLA 700 Series provides a solution by allowing you to monitor, capture and analyze real-time hardware operation. It does this is by enabling high-speed timing and deep state acquisition at the same time on all channels through the same probe.

Unprecedented levels of resolution, state acquisition and timing analysis, enabled by MagniVu acquisition technology, are shown in the following measurement capabilities:

• 500 ps Timing Resolution on All Channels
  By storing timing information in MagniVu acquisition technology's high-speed memory at the full 2 GHz rate, all TLA 700 Series logic analyzers can offer 500 ps timing resolution on all channels, all the time.
• Up to 200 MHz State Acquisition With Up to 400 MHz Data Rate
  TLA 700 Series modules offer standard configurations with state acquisition up to 100 MHz for common applications and optional 200 MHz configurations for leading-edge applications. Since all clocks and data are oversampled at a 2 GHz rate and processed in real-time to provide 200 MHz synchronous acquisition, each data sample is timestamped with 500 ps resolution.
  Even high-speed double-pumped buses can be easily supported with data rates up to 400 MHz.
• Simultaneous State and Timing Analysis Through the Same Probes
  The logic analyzer modules are able to provide both timing analysis and state acquisition simultaneously. They provide 500 ps timing and up to 200 MHz state acquisition at the same time, through the same probes.
  You no longer have to connect a second set of probes and timing modules to a bus that you're already acquiring state data from. No more running out of timing channels because you didn't have enough modules or couldn't fit them into your logic analyzer. No tradeoffs of channels or important features to get the results you need.

TLA microprocessor support provides you with an easy-to-use acquisition and analysis package. The software automatically sets up the TLA, including assigning channels and programming the clocking state machine for your particular processor. This allows the TLA to acquire every bus cycle in real-time without interfering with full-speed operation of the processor bus. Many of the support packages provide a probe adapter to aid connection to the processor or bus being analyzed.

Real-time software problems such as crashes, memory leaks and stack overruns are hard to debug because they only occur when the system is running "at speed." The TLA 700 Series features extremely deep memory, which allows you to perform a "real-time trace" on a large time interval to identify the problem. Real-time trace records the activity of the program without stopping execution.

The logic analyzer acquisition modules for the TLA 700 Series provide up to an unprecedented 16 Mb of data per channel, with timestamps. The TLA 700 Series employs an innovative proprietary hardware-assisted engine that can search or compress the entire contents of a 16 Mb deep acquisition in a fraction of the time it takes conventional logic analyzers to process much smaller quantities of data. This sampling depth allows you to rapidly track down complex problems, often when the symptoms are not visible until long after the data is corrupted and the damage is done.

Hardware and software designers need the ability to generate digital stimuli to simulate infrequently encountered test conditions in hardware design and software program testing. The pattern generator enables you to easily perform functional verification, debugging and stress testing for system hardware design. This multi-channel, programmable pattern-generator module with sequential control stimulates the prototype with data from the simulator for extended analysis. It makes the powerful acquisition technology of the TLA 700 Series accessible to design engineers who require an integrated pattern generation solution.

The pattern generator is ideal for designing systems where surrounding boards, ICs or buses that normally provide data signals to the device under test are missing. With the pattern generator, you can place the circuit in a desired state, operate it at full speed, or single-step it through a series of states. The pattern generator features up to 64 channels and supports up to a 268 MHz clock rate for data output. It achieves high performance with speeds of 268 million vectors per second and up to 2 Mb of memory per channel. This performance allows the pattern generator to test designs at speed through full performance up to the specified maximum clock rate.

The TLA 600 and TLA 700 Series logic analyzers capture waveform data in a form that can be read by SynaptiCAD^TM WaveFormer Pro^TM, VeriLogger Pro^TM, and TestBencher Pro^TM software tools. SynaptiCAD's tools can convert the logic analyzer waveform data into stimulus vectors for VHDL, Verilog, SPICE, ABEL, and pattern generators including the TLA 7PG2. This functionality gives engineers the ability to leverage the work done during the design phase of the product, simplifying the development of a hardware test environment that provides complete test coverage and excellent debug capability.

The TLA 7PG2 Pattern Generator stimulus can be created from a mixture of VHDL and Verilog test benches, simulation waveforms, real world data acquired by a logic analyzer, and waveforms created within SynaptiCAD's timing diagram editing environment.

The TLA 700 Series offers a range of digitizing oscilloscope modules that provide the acquisition capabilities of the world's best digitizing oscilloscopes, tightly integrated with the TLA 700 logic analyzers.

Tektronix wrote the book on oscilloscopes and Digital Real-Time^TM technology, which brings the bandwidth of leading analog oscilloscopes to single-shot digital applications. The 2- and 4-channel digitizing oscilloscope modules available in the TLA 700 Series offer sample rates of up to 5 GS/s and bandwidths of up to 1 GHz, with 15 K per channel at all times.

The digitizing oscilloscope modules offer precise time correlation and flexible cross-triggering with the other installed modules. This enables you to see the quality of critical signals alongside the digital behavior they affect.

These modules offer the triggering you expect from a Tektronix digital oscilloscope: Pulse Width, Runt, Glitch, Slew Rate, Logic Pattern, Setup-and-Hold Violation, Edge and Timeout. All trigger modes can be fully time-qualified for any period from 2 ns to 1 s and are easily set up with a Microsoft Windows user interface.

The High Level Language (HLL) Source Code Support post-processes real-time trace data acquired from processors and buses and automatically correlates it with your high-level language source code. It uses the information provided in the object file from your compiler to build a database of source files, line numbers and symbolic information.

Each time you acquire real-time data with your logic analyzer, you can view the acquired data disassembled in the Listing Window. This shows how your code was executed in native assembly language, or at the source code level in the Source Window, which shows your code as written in the high level language you use. You can step forward or backward through your source code and view the underlying assembly code or vice versa, using the global cursors. Multi-processor and bus systems are supported via multiple Source and Listing Windows, all automatically time-correlated.

The HLL Source Code Support is standard on all Tektronix logic analyzers. It is a non-intrusive tool that supports any high-level language whose software tools produce supported object-file formats. There's no need to modify or instrument your source code. Refer to the Mainframe Characteristics section for the number of symbols and object file formats supported.

Problems like slow software execution and unoptimized code can degrade system performance. These and other problems call for solutions to optimize hardware and software designs. With its robust performance analysis tools, the TLA 700 Series can help you find and fix problems by monitoring, capturing and analyzing real-time hardware and software performance.

Performance Analysis generates statistical representations by post-processing real-time data acquired from processors and buses connected to the logic analyzer module and displaying the results in a Histogram window. You can sort the display in either ascending or descending order. You can also export the results for further analysis.

You can view the results acquired by two different methods:

• State Overview: Select a channel group such as Address, set up your ranges either manually or automatically by loading symbols from your object module and press Run to monitor the number of hits against each range
• Single Event: Select a timer (or counter), set up the time intervals either linearly or logarithmically and press Run to monitor the varying time (with 4 ns resolution) over multiple acquisitions

As with the HLL Source Code Support, the Performance Analysis is a non-intrusive tool. There's no need to instrument or modify your source code.

The Performance Analysis is standard on all TLA 700 logic analyzers. It utilizes the same symbols in the TLA 700's symbolic database. Refer to the Mainframe Characteristics section for the number of symbols and object file formats supported.

The TLA 700 Series offers features that will increase your productivity as well as free you to work on higher priorities. By employing a true open systems architecture with its Microsoft Windows operating system, the TLA 700 Series allows you and the tools you rely on every day to work in a more familiar, connected environment.

You and your design team can set up the TLA 700 Series quickly. Once set up, it's easy and fast to operate as well. Speedy operation continues with the help of the high-density probes, the ability to save data and setups over a network and remotely view logic analyzer data, to name just a few features. Additionally, the TLA 700 Series offers leading-edge hardware-accelerated waveform display and search on deep acquisitions.

It's also easy to connect software development tools such as compilers and software debuggers/emulators to run on the TLA 700 Series. The combination of these tools with the TLA 700 Series running on the Microsoft Windows operating system provides a powerful, compact tool environment that reduces design cycle time. The open platform allows you to seamlessly integrate the TLA 700 Series with other networked applications, even control the instrument remotely via a Web browser. It's easy to install design documentation and analysis tools on the TLA 700 Series to view design specifications and provide a simple way to acquire and create system operation documentation

The TLA 700 Series mainframes offer a new paradigm for test instrumentation. Instead of building a proprietary compute engine into an instrument, Tektronix uses an industry-standard computer and operating system. You can install industry-leading software debuggers and run control interfaces on the TLA 700 Series to download and run code on your target. You can view your data on either the 800 x 600 internal flat-panel display (TLA 714 only) or with an external monitor with up to 1600 x 1200 (both TLA 714 and TLA 720) resolution.

Both the portable TLA 714 and the benchtop TLA 720 run on Microsoft Windows, so you save time navigating the familiar user-interface. Because Windows is fully integrated and embedded when you open the box, you get the benefit of a familiar environment without having to set things up yourself. This allows you to concentrate on the problem you're solving rather than the tool you're using.

You also don't have to worry about how to integrate the TLA 700 into your design environment. Any accessories you can buy that connect a portable PC into your environment can be used directly on TLA 700 Series mainframes. Standard USB, PS2 mouse and keyboard, serial, parallel, SVGA, and PC Card (CardBus) interfaces are used for external accessories. The TLA 700 Series comes standard with 3.5-inch floppy, CD-ROM and replaceable hard drive.

All modules, software, and accessories are fully interchangeable between portable and benchtop mainframes.

The TLA 700 Series can repeatedly acquire data from your target system and perform a variety of operations depending on the comparison results. At each iteration, you can either save the results and restart, or stop and send a command that could alert you via e-mail or pager. Then, you can save the results, concatenate to a single file or specify that each new file has the filename autoincremented.

The TLA 700 can automatically compare the results of repeated acquisitions to a reference acquisition and highlight the differences in either Listing or Waveform Windows. You can specify the range of samples over which to make the comparison or specify the offset. You can also mask or prevent channels from being compared.

It's possible as well to set up your TLA 700 Series to continuously monitor your target system, thereby freeing you for other tasks and notifying you only when there's an anomaly.

Using Microsoft Windows Component Object Model (COM/DCOM) technology, the TLA 700 Series Programmatic Interface (TPI) provides next-generation technology for logic analyzer remote control. The TPI provides a modern function call interface that is compatible with COM/DCOM programmatic interfaces of other Windows applications. Support for non-Windows platforms (e.g., UNIX) is available as well. Basic scripting capability is provided by the TLA 700's TLAScript.

The TPI supports the following remote operations:

• System: Configuration, Load/Save, Run Control, Status & Errors
• Logic Analyzer Module: Load/Save, Trigger Setup, Acquisition Data & Parameters
• Pattern Generator Module: Load/Save, Acquisition Data & Parameters
• Digitizing Oscilloscope Module: Load/Save, Acquisition Data & Parameters

With TPI you can spend less time trying to build advanced data analysis from scratch and instead use existing Windows applications such as Microsoft Excel, Microsoft Visual Basic or C++ to build an advanced data analysis application that seamlessly integrates with the TLA 700 Series. You can then run your application directly on the TLA 700 Series or from a computer connected via LAN to your TLA 700 Series.

TLAVu^TM and PatGenVu^TM provide you with the ability to view your TLA data offline on your own Windows PC away from the lab in the comfort of your own office or cubicle. TLAVu is a version of the TLA application software that you can install on a Windows 95, 98, NT4 or 2000 PC. PatGenVu is the equivalent for the TLA 7PG2 Pattern Generator application software.

Install TLAVu on your PC and use it to analyze the data that you've acquired on your TLA logic analyzer. Or you can send the TLA data directly to your colleagues or suppliers - instead of sending screen shots or Faxes - so they can interactively view the data using TLAVu on their own PCs.

You can also use TLAVu to create TLA setups for later use on your TLA in the lab. Just load a previously saved TLA system file from your TLA to automatically set the TLAVu hardware configuration, then create and save your new setups.

Both TLAVu and PatGenVu are distributed standard with every TLA logic analyzer beginning with Version 3.2 of the TLA Application Software. For existing TLA customers, both TLAVu and PatGenVu are available as no-charge downloads from www.tektronix.com/LA under the Software and Drivers section or for a small fee by ordering the TLA 6UP or TLA 7UP Field Upgrade Kits from your local Tektronix Account Manager. TLAVu is compatible with both TLA 600 and TLA 700 Series logic analyzers.

In the world of high-end design test, you need solutions that allow you to preserve your investment in existing equipment, buy only what you need now, and expand and upgrade easily when needs or technologies change in the future. Tektronix has built the TLA 700 Series with these needs in mind.

One example of this thinking is the TLA 700 Series expansion mainframe, which addresses the complex verification challenges associated with high-end computer and embedded systems design. It supports large channel-count applications that address current and future system needs. With expansion mainframes, the TLA 700 Series provides up to 16 total modules for a maximum of 2,176 analyzer, 1,024 pattern-generator or 64 digital storage oscilloscope channels.

The TLA 700 Series offers a high degree of modularity, with a wide range of digital, analog and software real-time acquisition and stimulus capabilities. Modularity means you pay only for the capability you need now while knowing you can expand capacity in the future. Regardless of whether you're designing cell phones or multi-processor Internet servers, you can scale your TLA 700 Series solution exactly to your application requirements.

Compatibility helps you preserve your investment now and into the future. Modules are compatible in all mainframes. Older modules can be used in new mainframes, and older mainframes can be upgraded to accommodate new modules. Additionally, both new and old modules can be used at the same time in the same mainframe. You can also upgrade the state speed and memory depth on your logic analyzer modules and the memory depth on your pattern generator module.

The TLA 700 Series, as with all Tektronix products, comes with the backing of the best service and support in the industry. You get free Application Engineer support at 1-800-TEKWIDE, application tools such as processor and bus supports, and other resources that add value to your investment. Please refer to the TLA Family Upgrade Guide for further details.

Tektronix TLA 700 Series logic analyzers offer breakthrough solutions for real-time digital systems analysis. Designed to meet the critical time and productivity needs of today's digital design engineers, the TLA 700 Series logic analyzers provide ideal solutions for hardware debug and verification, processor/bus debug and verification, embedded software integration, debug and verification, embedded real-time software optimization and system validation. High connectivity, modularity, compatibility and flexibility make the TLA 700 Series a solid investment for your needs today and tomorrow.

• MagniVu^TM Acquisition Technology Provides 500 ps Timing Resolution on All Channels All the Time Through a Single Probe
• Up to 200 MHz State Acquisition with 400 MHz Data Rate Supports Advanced Processors and Buses
• Simultaneous State and High Speed Timing Analysis Through the Same Probes Pinpoints Elusive Integration Faults
• Broad Selection of Processor and Bus Support
• Up to 16 Mbits Per Channel with Hardware-accelerated Waveform Display and Search Functions to Rapidly Analyze Large Amounts of Data to Find Elusive Problems Far Back in Time
• 64 Channel Pattern Generator with up to 268 MHz and up to 2 MB Memory Depth Provides Digital Stimulus for Functional Verification, Debugging and Stress Testing
• Four Channel Digitizing Oscilloscope with up to 1 GHz, 5 GS/s Provides High-fidelity Signal Quality Measurements of Digital Signals
• Expansion Mainframe Supports up to 16 Modules with up to 2,176 LA channels, 1,024 Pattern Generator Channels or 64 Digitizing Oscilloscope channels for Large, Multiple Processor and Bus Applications
• Universal HLL Source Code Support for Correlating High-level Language Source with Real-time Trace
• Performance Analysis Support for Optimizing Target System Performance
• Remote Control Using Microsoft COM/DCOM Technology Supports Advanced Data Analysis
• Microsoft® Windows®-based PC Platform Provides Familiar User Interface With Network Connectivity
• All Modules, Probes, Software and Accessories Fully Interchangeable Between Portable and Benchtop Mainframes with Flexibility for Future Upgrades To Protect Your Investment

• Hardware Debug and Verification
• Processor/Bus Debug and Verification
• Embedded Software Integration, Debug and Verification
• Embedded Real-time Software Optimization
• System Validation

Specifications

Number of Channels per Module (all channels are acquired including clocks) -
TLA 7N1: 34 channels (2 are clock/qualifier channels).
TLA 7N2, TLA 7P2: 68 channels (4 are clock/qualifier channels).
TLA 7N3: 102 channels (4 are clock/qualifier and 2 are qualifier channels).
TLA 7N4, TLA 7P4: 136 channels (4 are clock/qualifier and 4 are qualifier channels).
Channel Grouping - No limit to number of groups or number of channels per group (all channels can be reused in multiple groups).

Module "Merging" - Three 102 channel or 136 channel modules can be "merged" to make up to a 408 channel module. Merged modules exhibit the same depth as the lesser of the three individual modules. Word/range/setup-and-hold/glitch/transition recognizers span all three modules. Only one set of clock connections is required.

Time Stamp - 50 Bits at 500 ps resolution (6.5 day range).

Clocking/Acquisition Modes- State, timing, simultaneous.

Number of Mainframe Slots Required - 2. 

Capacitive Loading -
1.4 pF typical data; 2 pF typical clock (P6418).
2 pF typical (P6417 & P6434).

Threshold Selection Range - From +5.0 V to -2.0 V in 50 mV increments.

Threshold Selection Channel Granularity - Separate selection for clock (1) and data (16) for each 17 channel probe connector.

Threshold Accuracy (including probe) - ±100 mV.

Input Voltage Range -
Operating: 6.5 V_P-P centered around the programmed threshold.
Non-destructive: ±15 V.

Input Signal Swing (probe overdrive) -
±250 mV or ±25% of signal swing, whichever is greater (P6417 & P6418).
±300 mV or ± 25% of signal swing (P6434).

Input Signal Minimum Slew Rate - 200 mV/ns typical.

Maximum Synchronous Clock Rate - 100 MHz standard, 200 MHz optional.

Maximum Data Rate (Half Channels) - 400 MHz, typical. Requires 200 MHz state option.

State Memory Depth - 64 K, 256 K, 1 M, 4 M or 16 M bits per channel.

Setup Time Selection Range - From 8.5 ns before, to 7.0 ns after clock edge.

Setup-and-hold Window - 2.0 ns typical.

Minimum Clock Pulse Width - 2 ns.

Active Clock Edge Separation - 5 ns.

Demux Channel Selection - 32 channels can be demultiplexed to other channels through user interface; for all channels contact local Tektronix account manager.

Main Timing Resolution - 4 ns to 50 ms.

Main Timing Resolution with Glitch Storage Enabled - 10 ns to 50 ms.

Main Timing Memory Depth (with or without transitional storage enabled) - 64 K, 256 K, 1 M, 4 M or 16 M bits per channel.

Main Timing Memory Depth with Glitch Storage Enabled - Half of default main memory depth.

MagniVu - 500 ps.

MagniVu Timing Memory Depth - 2 Kbits (2048) per channel.

Channel-to-channel Skew - <1 ns typical.

Minimum Recognizable Pulse Width (single channel) - 2 ns.

Minimum Recognizable Glitch Width (single channel) - 2 ns.

Minimum Recognizable Multi-channel Trigger Event - Sample period + 2 ns.

Independent Trigger States - 16.

Maximum Independent If/then Clauses per State - 16.

Maximum Number of Events per If/then Clause - 8.

Maximum Number of Actions per If/then Clause - 8.

Maximum Number of Trigger Events - 18 (2 counter/timers plus any 16 other resources).

Number of Word Recognizers - 16.

Number of Range Recognizers - 4.

Number of Counter/Timers - 2.

Trigger Event Types - Word, group, channel, transition, range, anything, counter value, timer value, signal, glitch, setup-and-hold violation.

Trigger Action Types - Trigger module, trigger all, store, don't store, start store, stop store, increment counter, reset counter, start timer, stop timer, reset timer, goto state, set/clear signal, do nothing.

Trigger Sequence Rate - DC to 250 MHz (4 ns).

Counter/Timer Range - 51 bits each (>100 days @ 4 ns).

Counter Rate - DC to 250 MHz (4 ns).

Timer Clock Rate - 250 MHz (4 ns).

Counter/Timer Latency - None (can be tested or reset immediately after starting).

Range Recognizers - Double bounded (can be as wide as any group, must be grouped according to specified order of significance).

Setup-and-hold Violation Recognizer Setup Time Range - From 8 ns before to 7 ns after clock edge in 0.5 ns increments.

Setup-and-hold Violation Recognizer Hold Time Range - From 7 ns before to 8 ns after clock edge in 0.5 ns increments.

Trigger Position - Any data sample.

MagniVu^TM Trigger Position - MagniVu data is centered around the module trigger.

Storage Control (data qualification) - Global (conditional), by state (start/stop), by trigger action, or transitional.

Storage Window Granularity - Single sample or block-of-31 samples before and after.

P6417 Probe Cable Length - 1.8 m (6 ft.).

P6418 Probe Cable Length - 1.9 m (6.25 ft.).

P6434 Probe Cable Length - 1.5 m (5 ft.).
All three probes have the same electrical length.

Data Width -
64 Channel full channel mode.
32 Channel half channel mode.

Module "Merging" - Five modules can be "merged" to make up to a 320 channel module. Merged modules exhibit the same depth as the lesser of the 5 individual modules.

Number of mainframe slots required - 2. 

Data Rate -
Internal Clock:

External Clock:

External Clock Input -
Polarity: positive or negative.
Threshold: -2.56 V to +2.54 V, nominal; programmable in 20 mV increments.
Sensitivity: <500 mV_p-p.
Impedance: 1 kilohm terminated to ground.

Data Depth -
256 K full channel/512 K half channel.
1 M full channel/2 M half channel (optional).

Blocks - Separate sections of pattern program that are output in a user definable order by the Sequencer. Block pattern depth can be from 40 sequences (full channel mode) or 80 sequences (half channel mode) up to the entire depth of the TLA 7PG2. A maximum of 4,000 Blocks may be defined.

Sequencer - A 4000 line memory that allows the user to pick the output order of individual Blocks. Each line in the sequencer allows the definition of a Block to be output, a Repeat Count for that Block, A Wait For event condition for the Block, the Signal state for that Block (asserted or unasserted), and a Jump If event condition, with a sequence line to jump to if the condition is satisfied.

Sub-Sequences - Up to 50 contiguous lines of the Sequencer memory may be defined as a Sub-Sequence. A Sub-Sequence can then be treated like a block. (Example: 15 Sequences of Blocks are defined as Sub-Sequence A1. Now any line in the Sequencer can output A1. Five calls to Sub-Sequence A1 will be flattened out to 75 sequences at run time.)

Jump If - Jumps to the specified sequence if a user defined event is true. The user defined event is a boolean combination of the eight external event input lines and the one-of-four intermodule signals. The user defined Event is selectable between level and edge (event going from false to true). One Jump If may be defined for every Block. The Jump If command works at all clock rates, including the maximum half channel mode rate of 268 MHz.

Wait For - Pattern output is paused until the user defined Event is true. One Wait For may be defined for every Block.

Assert Signal - One of the four inter-module signals is selected to be controlled from the pattern generator program. Signals may be asserted and unasserted allowing true interaction with the logic analyzer modules and with other pattern generator modules. Signal action (assert or unassert) may be defined for every Block.

Repeat Count - The sequence is repeated from 1 to 65,536 times. Infinite may also be selected. One Repeat Count may be defined for every Block. Note that a Repeat value of 10,000 takes one sequence line in memory, not 10,000.

Step - While in Step mode, the TLA 7PG2, the user can manually satisfy (i.e., click an icon) Wait For and Jump conditional events. This allows the user to debug the logic flow of the program's sequencing.

Initialization Block - The unconditional Jump command allows the user to implement an equivalent function.

Number of Data Outputs -
16 in Full Channel Mode.
8 in Half Channel Mode.

Number of Clock Outputs - 1. 
(Only one of Clock Output and Strobe Output can be enabled.)

Number of Strobe Outputs - 1. 
(Only one of Clock Output and Strobe Output can be enabled.)

Number of External Event Input - 2. 

Clock Output Polarity - Positive.

Strobe Type - RZ only.

Strobe Delay - Zero or Trailing Edge.

Output Type -
HD74LVC541A for Data Output.
HD74LVC244A for Clock/Strobe Output.

Rise/Fall Time (20% to 80%) -

Output Voltage (nominal, load: 1 megaohm) -
V_OH: 2.0 V to 5.5 V, tri-stateable, programmable in 25 mV increments.
V_OL: 0 V.

Data Output Skew -
< 510 ps typical between all data output pins of all modules in the mainframe after inter-module skew is adjusted manually.
< 480 ps typical between all data output pins of single probe.

Data Output to Strobe Output Delay - 1.7 ns typical when strobe delay set to zero.

Data Output to Clock Output Delay - 2.4 ns typical.

External Clock Input to Clock Output Delay -
Full Channel mode: 61.5 ns typical.
Half Channel mode: 61.5 ns typical.

Number of External Inhibit Input - 1. 

External Inhibit Input to Output Enable Delay - 34 ns typical for Data Output.

External Inhibit Input to Output Disable Delay - 86 ns typical for Data Output.

Probe D Data Output to Output Enable Delay - (for Internal Inhibit) 7 ns typical for Data Output.

Probe D Data Output to Output Disable Delay - (for Internal Inhibit) 8 ns typical for Data Output.

External Event Input to Clock Output Setup (for inhibit) (event-filter: off) -
Full Channel mode: 1.5 clocks + 150 ns typical.
Half Channel mode: 2 clocks + 150 ns typical.

External Event Input and Inhibit Input -
Input Type: 74LVC14A.
Minimum Pulse Width: 100 ns.

Output Type -
100E151 for data output.
100EL16 for strobe output.
100EL04 for clock output.
All outputs are unterminated.

Rise/Fall Time (20% to 80%) -

Data Output Skew -
< 170 ps typical between all data output pins of all modules in the mainframe after inter-module skew is adjusted manually.
< 140 ps typical between all data output pins of single probe.

Data Output to Strobe Output Delay - 2.94 ns typical when strobe delay set to zero.

Data Output to Clock Output Delay - 780 ps typical.

External Clock Input to Clock Output Delay - 51 ns typical.

External Event Input -
Input Level: ECL.
Input Type: 10H116.
Minimum Pulse Width: 50 ns.

P6470 Probe Cable Length - 1.6 m (5 ft.)

P6471 Probe Cable Length - 1.6 m (5 ft.)

Number of Channels per Module -
TLA 7D2, TLA 7E2: 4 channels.
TLA 7D1, TLA 7E1: 2 channels.

Sample Rate -
TLA 7E1, TLA 7E2: 5 GS/s on all channels.
TLA 7D1, TLA 7D2: 2.5 GS/s on all channels.

Bandwidth (at probe tips) -
TLA 7E1, TLA 7E2:

All others:

Memory Depth -
15,000 samples per channel in all modes.

Number of Mainframe Slots Required - 2.

Input Sensitivity Range - 10 mV to 100 V full scale.

Vertical Resolution - 8 bits (256 levels).

DC Gain Accuracy - ±1.5% of full scale range.

Analog Bandwidth Selections - 20 MHz, 250 MHz, and Full.

Input Coupling - AC, DC, or GND.

Input Impedance Selections - 1 megaohm in parallel with 10 pF, or 50 Ohm.

AC Coupled Lower Frequency Limit - <10 Hz when AC 1 megaohm coupled, <200 kHz when AC 50 Ohm coupled.

Maximum Input Voltage at Probe Connector - 300 VRMS, but no greater than ±420 V peak (1 megaohm or ground input coupling).

Probe Input Interface - TEKPROBE® probe interface.

Input Loading - Less than 1 pF in parallel with 1 megaohm with either P6243 or P6245.

Usable Input Voltage Range at Probe Tip - P6243 Probe: ±8 V. P6245 Probe: ±18 V.

Sample Rate Range - 200 ps to 200 ms in 1, 2.5, 5 sequence.

Timebase Accuracy - ±100 ppm over any interval >1 ms.

Record Length Range - 512 to 15,000 samples per channel in all modes.

Acquisition Modes - Single-shot, repetitive.

Trigger Modes - Normal, auto.

Trigger Position - Anywhere in the acquired record (pre-fill can be set anywhere from 0% to 100%).

Trigger Types - Edge, pulse width, timeout, glitch, runt, slew rate, logic pattern, setup-and-hold violation.

Trigger Actions - Trigger, trigger all, set signal, arm, immediate, wait for system trigger.