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Recommended
Model Numbers |
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Key Options |
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Details |
| Agilent 16800 Series Portable Logic Analzyers |
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16801A
16802A
16803A
16804A
16806A
16821A
16822A
16823A |
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15 inch color display with available touch screen - View relationships between large numbers of
signals and busses to identify a problem sooner |
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Pattern generator - Get stimulus and response in a single instrument with the only portable logic analyzer to include a built-in pattern generator |
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32 M Deep memory - Capture symptom and root cause that are widely separated in time |
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Up to 204 channels |
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Upgradeable memory depth and state speed - Purchase the capability you need now, then upgrade as your needs evolve |
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ViewScope - Seamless, correlated measurements between oscilloscopes and logic analyzers |
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| Agilent
DSO80000B Series Infiniium Oscilloscopes |
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DSO80204B
DSO80304B
DSO80404B
DSO80604B |
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Need compatible probes/cables |
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Up to 40 GSa/s sample rate |
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p to 2 Mpts MegaZoom deep memory at 40 GSa/s, 64 Mpts at 4 GSa/s |
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Industry's lowest noise floor for both oscilloscopes and probes |
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Industry's lowest jitter measurement floor |
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Industry's lowest trigger jitter - less than 500 fs rms |
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Industry's flattest frequency response |
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Upgradeable Bandwidth |
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Industry's largest selection of application software packages |
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| Agilent 8000 Series Infiniium Oscilloscopes |
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DSO8064A
DSO8104A
MSO8064A
MSO8104A |
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High-performance mixed-signal oscilloscopes (with MSO Series scope) provide deep memory and powerful triggering for verifying FPGA technology designs. |
| Agilent 6000 Series Oscilloscopes |
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DSO6032A
DSO6034A
DSO6052A
DSO6054A
DSO6102A
DSO6104A
MSO6032A
MSO6034A
MSO6052A
MSO6054A
MSO6102A
MSO6104A
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Mid-performance portable mixed-signal oscilloscopes (with MSO Series scope) provide deep memory and powerful triggering for verifying FPGA technology designs. |
| Agilent
FPGA Dynamic Probes |
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B4655A
B4656A
N5406A |
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Access up to 64 internal signals for each pin dedicated to debug |
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Switch internal probe points in seconds without changing your FPGA design |
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B4655A supports Xilinx Virtex-5 series, Virtex-4 series, Virtex-II Pro series, Virtex-II series, and Spartan-3 series devices |
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B4656A supports Altera devices: Stratix series, Cyclone series, MAX series, APEX series, and Excalibur series |
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| Agilent
Logic Analyzer Probes |
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E5339A
E5346A
E5351A
E5383A
E5385A
E5394A
E5396A
E5404A |
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Wide variety of probing accessories that support general-purpose and application-specific measurement needs |
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Easy to connect your Agilent logic analyzer to your system under test |
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Sold separately from logic analyzers |
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| Agilent
81133/34A Pulse Pattern Generator
- 15 MHz to 3.35 GHz, 2 channel |
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81133A
81134A |
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Provide programmable pulse periods from 15 MHz (66.6 ns) to 3.35 GHz (298.5 ps) on all channels
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1 channel (81133A) or 2 channels (81134A) |
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Pulse, Data Pattern and PRBS generation from 15 MHz up to 3.35 GHz |
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Data formats NRZ, RZ and R1 |
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12 Mbit pattern memory per channel |
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Low jitter, high accuracy |
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Fast transition times |
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Xilinx ChipScope Pro Software |
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ChipScope Pro |
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Required for FPGA Dynamic probe |
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Link to Agilent Technologies logic analyzers using, for more robust verification, including cross-correlating signals from inside the FPGA to elsewhere on the board |
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Analyze any internal FPGA signal, including embedded processor busses |
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Inserts low-profile, configurable software cores either during design capture, or after synthesis |
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Leveraging FPGA reprogrammability, identify problems and change your design in minutes or hours, not weeks or months as in traditional ASIC desig |
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Altera Quartus II Software |
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Quartus II |
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Required for FPGA Dynamic probe |
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TimeQuest timing analyzer is a new, next-generation ASIC-strength timing analyzer supporting the
industry-standard Synopsys Design Constraints (SDC)-based timing analysis methodology |
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# PowerPlay power analysis and optimization technology provides automated power optimization capabilities and helps you effectively manage power from design concept through implementation |
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Incremental compilation supports the bottom-up design flow that allows design blocks to be created and optimized independently. System architects can incrementally integrate optimized design blocks while the performance of the design blocks is preserved throughout the integration process |
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