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 Tektronix TLA Family Logic Analyzer Selection Guide

 Applications

   

TLA6xx

TLA715

TLA721

Timing and State Analysis

Yes

Yes

Yes

Single-processor/Bus Analysis

Yes

Yes

Yes

Real-time Instruction Trace Analysis

Yes

Yes

Yes

Source Code Debug

Yes

Yes

Yes

Performance Analysis

Yes

Yes

Yes

Multi-processor/Bus Analysis

   

Yes

Yes

Digital Stimulus and Control

   

Yes

Yes

Digital Signal Quality Analysis

Yes

Yes

Yes

System Validation

   

   

Yes

 TLA Mainframe Selection

   

TLA6xx

TLA715

TLA721

TLA7XM

Type of Mainframe

Non-modular

Modular

Modular

Expansion - Modular

Number of module slots

N/A

2

5

6

Operating System

Microsoft® Windows 2000 Professional

Microsoft® Windows 2000 Professional

Microsoft® Windows 2000 Professional

N/A

Internal Display Resolution

800x600 (TLA61x/62x only; TLA60x requires external display)

800x600

Requires external display

N/A

External Display Resolution

1280x1024

1600x1200

1600x1200

N/A

Number of External Displays

1

4 (with two PCMCIA video adapters)

4 (with two PCMCIA video adapters)

N/A

Standard Data Window Types

Waveform, Listing, Histogram (Performance Analysis), Source Code

Waveform, Listing, Histogram (Performance Analysis), Source Code

Waveform, Listing, Histogram (Performance Analysis), Source Code

N/A

Remote Control with Microsoft COM/DCOM

Yes

Yes

Yes

N/A

 TLA Logic Analyzer Selection

   

TLA6xx

TLA7Nx/Px/Qx

TLA7Axx

Channels

34, 68, 102, 136 per instrument

34, 68, 102, 136 per module

34, 68, 102, 136 per module

Max Channels per Timebase (merged)

136

272 in TLA715 408 in TLA721

272 in TLA715 680 in TLA721

Max Channels per Mainframe

136

272 in TLA715 680 in TLA721

272 in TLA715 680 in TLA721

Max Channels per System

136

1,768 (with TLA715 and two TLA7XMs) 8,160 (with TLA721 and ten TLA7XMs)

1,768 (with TLA715 and two TLA7XMs) 8,160 (with TLA721 and ten TLA7XMs)

Max Independent Buses per System

1

13 (with TLA715 and two TLA7XMs) 60 (with TLA721 and ten TLA7XMs)

13 (with TLA715 and two TLA7XMs) 60 (with TLA721 and ten TLA7XMs)

State Clock Rate

100 MHz std. 200 MHz opt.

100 MHz std. 200 MHz opt.

120 MHz std. 235, 450 MHz opt.

Max State Clock Rate - half channel mode

200 MHz

200 MHz

800 MHz

Max State Data Rate

400/200 Mb/s (half/full channels)

400/200 Mb/s (half/full channels)

1,250/900/450 Mb/s (quarter/half/full channels)

MagniVu™ Timing (all channels, all the time)

2 GHz (500 ps) with 2 Kb depth

2 GHz (500 ps) with 2 Kb depth

8 GHz (125 ps) with 16 Kb depth

Simultaneous State and Timing Through Same Probe

Yes

Yes

Yes

Analog Measurements Through Same Probe

No

No

Yes

Deep Timing

500 MHz (2 ns)/250 MHz (4 ns) (half/full channels)

500 MHz (2 ns)/250 MHz (4 ns) (half/full channels)

2 GHz (500 ps)/1 GHz (1 ns)/500 MHz (2 ns) (quarter/half/full channels)

Memory Depth

128/64 Kb to 2/1 Mb (half/full channels with timestamp)

128/64 Kb to 128/64 Mb (half/full channels with timestamp)

512/256/128 Kb to 256/128/64 Mb (quarter/half/full channels with timestamp)

Source Synchronous Clocking

No

No

Yes

Analog Outputs (four per module - analog MUX)

No

No

Yes

 Digital Storage Oscilloscope Capability

   

TLA7Dx/Ex Modules
(Internal)

TDS Oscilloscopes (External)

Channels per Module

2 & 4

2 & 4

Max Channels per Mainframe

8 (TLA715) 20 (TLA721)

4

Max Channels per System

52 (with TLA715 and two TLA7XMs)
240 (with TLA721 and ten TLA7XMs)

4

Bandwidth

500 MHz & 1 GHz

100 MHz to 6 GHz

Sample Rate

2.5 GS/s & 5 GS/s

1.25 GS/s to 20 GS/s

Vertical Resolution

8-Bits

8-Bits and 9-Bits

Memory Depth

15 Kb

10 Kb to 32 Mb

 TLA Pattern Generator Module

   

TLA7PG2

Channels

64

Max Channels per Bus (merged)

128 (with TLA715) 320 (with TLA721)

Max Channels per Mainframe

128 (with TLA715) 320 (with TLA721)

Max Channels per System

832 (with TLA715 and two TLA7XMs) 3,840 (with TLA721 and ten TLA7XMs)

Pattern Speed (half/full channels)

268/134 MHz

Memory Depth (half/full channels)

512/256 Kb to 2/1 Mb

Logic Families Supported

CMOS/TTL, ECL, LVCMOS, PECL/LVPECL, LVDS, Variable

 
 
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